The present invention relates to the field of integrated circuit verification, and more specifically, to verifying the proper design and functionality of integrated circuits without using a xe2x80x9cgoldenxe2x80x9d model.
The proliferation of modem electronics into our everyday life is due in large part to the existence, functionality and relatively low cost of advanced integrated circuits. As technology moves ahead, the sophistication of integrated circuits has increased dramatically. However, dramatic increases in chip performance and complexity have also driven the need for improved methodologies to thoroughly and cost-effectively test the circuits and functions within the chip 1 as much as 30% to 50% of the total design effort. Designers recognize that faulty design verification can lead to expensive mask revisions and missed time-to-market deadlines.
When the industry was in its infancy, semiconductor designers relied primarily upon manually-generated test sequences for design verification. Test engineers selected functions to test and wrote test programs that provided pre-defined input stimuli to the function and compared the result with a precomputed expected response. This test methodology was slow and highly limited in that not every machine-state that the function may be exposed to during normal operation could be tested. Moreover, developing the test programs took a significant amount of time. Manually-generated tests are generally thought to be too hard to develop and too limited to be used as a primary design verification tool for today""s complex chip designs. Nevertheless, manually generated tests are still useful for very limited design verification, built-in-self-testing, and quality assurance testing in the manufacturing process.
Today""s chip designers employ a variety of different functional verification methodologies throughout the design process to insure that the design is on-track, including simulation, emulation, test generation, formal verification, and ASIC prototyping. These design verification methodologies have their advantages and disadvantages, but all share a common drawbackxe2x80x94they require a xe2x80x9cgolden model.xe2x80x9d A golden model is a working model or software simulation of the system being designed that, when provided with an input, produces a known-correct output. Since the golden model is (by definition) known to function in accordance with the chip""s design parameters, the output of the golden model is assumed to be correct. Designs are tested by providing identical inputs to the system under test and the golden model. If the output of the circuit or system under test is different from the output of the golden model when the circuit or system under test and the golden model are provided with the same input, system designers conclude that there is an error in the system under test that must be identified and corrected.
Although the use of a golden model as a verification tool is becoming more common in the industry, golden model-based verification is far from ideal. Developing an accurate golden model is expensive, time-consuming, and ties up valuable design resources. Golden models that are developed early enough in the design process to be useful for presilicon verification must be continually maintained and updated as the design evolves and as design verification progresses. If the golden model is developed using a commercially-available proprietary simulation language tool set (such as Verilog or VHDL), chip designers may gain the portability and interface advantages typically associated with an industry-standard tool, but may also incur high licensing fees and learning curve costs and delays. Golden models are typically orders of magnitude slower than the chips that they simulate, and therefore running simulations on the golden model consumes considerable time and computing resources. Finally, designers must always face the risk that their golden model contains unidentified errors that skew test results. Even error-free golden models may exhibit subtle, but ultimately important, behaviors that are different from the final chip design.
The present invention comprises a functional verification apparatus and methodology that enables rigorous random input-based design verification without the use of a golden model, thus providing chip designers all the advantages of random input-based design verification without the significant disadvantages associated with golden models.
The present invention is a method and apparatus that verifies the design and functionality of electronic circuitry without the use of a golden model. The designer tests circuitry that comprises a specified function by providing test input variables to the circuit under test, and inverse input variables to the circuitry comprising the inverse of the function under test. Depending upon the specific function under test, the input variables and inverse input variables may be randomlyxe2x80x94generated numerical values, or they may be variables or instructions selected to yield a specific result as compared to the expected result of the circuitry under test. The present invention exercises both the circuitry under test and the circuitry that is the inverse of the circuitry under test, collects and compares results, and provides an error notification when the comparison does not yield an expected result. If a designer receives an error notification, he is alerted to the possibility of an error condition in either the circuitry under test or in the inverse of the circuitry under test.